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Accelerating Artificial Intelligence with Programmable Silicon Photonics

Author(s)
Bandyopadhyay, Saumil
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Advisor
Englund, Dirk R.
Terms of use
In Copyright - Educational Use Permitted Copyright retained by author(s) https://rightsstatements.org/page/InC-EDU/1.0/
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Abstract
Advances in the fabrication of large-scale integrated silicon photonics have sparked interest in optical systems that process information at high speeds with ultra-low energy consumption. Photonic systems, which have historically been used for optical telecommunications, have recently been demonstrated to accelerate tasks in quantum simulation, artificial intelligence, and combinatorial optimization. This thesis reports work towards the goal of realizing large-scale programmable photonic systems for information processing: 1) we develop deterministic error correction algorithms for programmable photonic systems, whose capabilities are believed to be limited by fabrication error, showing that these systems can be programmed to implement accurate linear matrix processing suitable for deep neural networks at scales of up to hundreds of channels; 2) we describe a new paradigm for coupling large numbers of optical channels to photonic circuits with exceptionally high alignment tolerance, enabling the use of high-volume, low-precision electronic pick-and-place equipment for photonic assembly; and 3) we design, fabricate, and demonstrate the first single-chip, end-to-end photonic processor for deep neural networks. This fully-integrated coherent optical neural network (FICONN), which monolithically integrates multiple optical processor units for matrix algebra and nonlinear activation functions into a single chip, implements single-shot coherent optical processing of a deep neural network with sub-nanosecond latency. On-chip, in situ training of a deep neural network is demonstrated on this system, obtaining high accuracies on a vowel classification task comparable to that of a digital system. Our results open the path towards integrated, large-scale photonic processors for low-latency inference and training of deep neural networks.
Date issued
2023-06
URI
https://hdl.handle.net/1721.1/151430
Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Publisher
Massachusetts Institute of Technology

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