A Continuous-Time Pipeline ADC with Reduced Sensitivity to Clock Jitter

Abstract

With the advent of the fifth-generation (5G) standard for cellular networks, direct RF receivers are becoming popular in applications such as cellular base stations. Such systems require analog-to-digital converters (ADC) with a high dynamic range over a large digitization bandwidth (> 500 MHz). For high-speed high-resolution ADCs with an upfront sampler, the clock jitter poses a fundamental bottleneck for the maximum achievable signal-to-noise ratio (SNR). In applications requiring 10-12 bit resolution for 1 GHz digitization bandwidth, the clock jitter values must be no more than a few tens of femtoseconds. This poses significant design challenges for the clock generator.

The continuous-time (CT) pipeline ADC is an emerging architecture that combines the benefits of a discrete-time pipeline ADC and a continuous-time ∆Σ ADC architecture. In this thesis, we explore the clock jitter sensitivity of the CT pipeline ADC. We derive the SNR limitations in a CT pipeline ADC and propose a new CT pipeline ADC design with improved tolerance to clock jitter. We also present a design methodology for the delay line and propose a novel inductor-less delay line that provides a good amplitude and phase matching between the stage 1 signal path and the sub-ADC-DAC path from DC to 1.6 GHz to minimize the signal leakage in the first stage residue.

A prototype ADC was fabricated in a 16-nm FinFET process. The ADC achieves 61.7/60.8dB (low/high frequency) SNR over 1-GHz bandwidth. The active area is 0.77mm² and the ADC consumes 240mW. The Schreier figure-of-merit (FOMS) is 157.9dB which is amongst the best in comparison to other state-of-the-art continuous-time ADCs with digitization bandwidth greater than 500MHz.