Improving Macroscale Defect Detection in Semiconductor Manufacturing using Automated Inspection with Convolutional Neural Networks

Abstract

The work detailed in this thesis explores four distinct pathways of improving wafer macroscale defect detection from both tool-centric and operator-centric perspectives. The primary tool-centric improvement detailed in this work is the implementation of machine learning-enhanced defect detection models to provide recommendations of defective wafers to review operators. This work features the theory, data acquisition and processing, and training steps for three models designed to catch three different defect types. Models are trained on spin-on-glass (SOG) defects, defects around the perimeter of a wafer, and various other defects occurring in the central area of a wafer. SOG defects are the primary focus of this work, also occurring in the central area of a wafer, though much smaller than the defects present in the central defect detection model. After training, the SOG defect detection model achieved an area under curve (AUC) of 0.927 for testing data out of its training data set distribution. The edge model and general central model achieved AUC values of 0.906 and 0.909, respectively, also on out of distribution testing data. These models, and the tools developed for data labeling, can be adopted for automated defect detection, and efficient data tagging for machine learning applications.

The other improvement pathways featured in this work involve additional tool-centric improvements of examining and performing corrective action on current wafer inspection tools, and evaluating the potential for in-line wafer inspection during processing. An operator-centric improvement is also detailed, describing the feature, operational, and productivity enhancements associated with the development of a new software interface for wafer image review.