p-GaN Platform for Next-Generation GaN Complementary Transistors and Circuits

Abstract

Gallium nitride (GaN) integrated circuits (ICs) are receiving increasing attention because they offer compactness, reduced parasitics, and higher performance compared to discrete transistors or printed circuit board (PCB) integration. The p-GaN platform exhibits tremendous potential in power ICs and recently, in high temperature (500 °C) digital circuits. While the initial demonstrations offer promising results, several challenges remain. Notably, the lack of a monolithically integrated GaN complementary technology impedes the advancement of GaN power ICs.

This thesis aims to enhance the p-GaN platform (GaN-CMOS platform) (CMOS: complementary metal-oxide-semiconductor) through developing the next generation of GaN complementary technology (p-channel and n-channel field-effect transistors (FETs)). Based on the GaN-CMOS platform, the aggressive scaling of novel complementary transistors (self-aligned-gate p-FET and self-aligned metal/p-GaN-gate HEMT) is pursued. Alternative metallization schemes and a new technology for gate recess in GaN p-FETs are demonstrated. The unique characteristics of the p-FET are revealed through a combination of experimental measurements and TCAD simulations. The p-FET (based on GaN-CMOS platform) and p-GaN-gate n-FETs are analyzed for high temperature operation. Lastly, in order to aid the future design of more complex circuits based on the p-GaN platform, a device-to-circuit CAD framework was developed for GaN n-FET circuits and validated at high temperature up to 500 °C.

To the best of the author’s knowledge, the above results represent the state-of-the-art in GaN complementary technology and GaN electronics based on the p-GaN platform. These findings are expected to deliver wider impact in the areas of power, RF/mixed-signal, and high temperature electronics.