MLVR: Regular Expression-Based Specification for Verified Model Checking of Hardware

Abstract

Model checking is an approach to verification of finite-state systems which relies on iterating through all possible states and checking whether some condition holds at each state. One challenge with this approach is that in the majority of real-world systems, the number of states to traverse is too large to feasibly fully explore. In this thesis, we present MLVR (Multi-Layer Variable Regexp), a specification language designed for model checking against hardware system implementations. The syntax of MLVR is based on regular expressions, where we specify what traces of inputs and outputs from the system are acceptable. We offer support for variables to be remembered and later recalled, and we allow for treating the values of variables symbolically during model checking. This allows the state space of systems primarily dealing with variable input/output (for example, hardware buses) to be reduced enough that model checking is feasible for formal verification of the system. We provide a simplified language, SLVR (Single-Layer Variable Regexp), with some of the core features of MLVR and formal proofs of correctness for model checking with SLVR, implemented in the Coq proof assistant. The style and structure of the proofs about SLVR provide insight into how proofs of correctness of MLVR might be written, and they demonstrate solutions to some of the technical challenges raised in proving correctness of MLVR.