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Heterogeneous Integration of Spin-Photon Interfaces with s Scalable CMOS Platform

Author(s)
Li, Linsen
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Advisor
Englund, Dirk R.
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Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0) Copyright retained by author(s) https://creativecommons.org/licenses/by-nc-nd/4.0/
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Abstract
A central challenge in the development of long-range high-speed quantum networks and fault-tolerant quantum computing is the generation of a large-scale entanglement of quantum systems. Color centers in diamonds have emerged as a leading quantum information processing platform, satisfying the DiVincenzo criteria for quantum computing and recently enabling the quantum advantage in communications. However, it is estimated that for general-purpose quantum information processors, millions to billions of high-quality physical qubits will be required, motivating the need for hardware architectures that are highly scalable by leveraging modern semiconductor integrated systems. Here, we introduce a scalable quantum information processing hardware architecture in a proof-of-concept consisting of an addressable and tunable two-dimensional array of tin-vacancy centers, hybrid integrated on a foundry process electronics control chip. We demonstrate necessary components individually, like scalable high-yield heterogeneous integration between diamond nanostructure and foundry control chip, parallel control and measurement, tuning of quantum emitter emission wavelength as well as lifetime, and coherent light correlation with quantum emitters as a proof of concept for a scalable architecture capable of hosting thousands toward millions of qubits. Besides the experimental demonstration of the architecture, the thesis will include free-space spin-photon interface design, quantum emitter strain engineering, scalable high-quality fabrication technology, general architecture theoretical analysis, and AI-assistant quantum resource scheduling for a deep discussion of the different essential components of the system.
Date issued
2024-05
URI
https://hdl.handle.net/1721.1/156627
Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Publisher
Massachusetts Institute of Technology

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