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Energy-Efficient Real-Time Hardware Acceleration for Gaussian Fitting

Author(s)
Wojtyna, Adrianna D.
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Advisor
Sze, Vivienne
Terms of use
Attribution-NonCommercial-NoDerivatives 4.0 International (CC BY-NC-ND 4.0) Copyright retained by author(s) https://creativecommons.org/licenses/by-nc-nd/4.0/
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Abstract
Micro-robots play an important role in numerous tasks, including search and rescue, exploration, and navigation. A significant challenge to their deployment is their limited energy capacity, which constrains the computation such systems can complete. Specifically, 3D mapping algorithms significantly contribute to the compute power footprint as a result of repeated memory accesses. A promising approach involving Gaussian Mixture Models (GMMs), Single-Pass Gaussian Fitting (SPGF) algorithm, allowed for real-time 3D mapping with minimal memory and energy requirements due to its single-pass processing of input data. To further decrease demonstrated energy results, we propose the design of an FPGA (Field Programmable Gate Array)-based hardware accelerator that enables Gaussian fitting based on the SPGF algorithm with 10.4× lower energy per image (based on post-implementation power analysis), compared to the original, software implementation. By using fixed-point numerical representation and concurrent processing of data inputs, our proposed hardware accelerator, when operating at 100MHz, is capable of processing depth images at an average rate of 303.09 frames per second (fps), allowing for 7.97× improvement compared to the original software implementation of SPGF (32fps). We also demonstrated 46.1× lower average FPGA resource utilization compared to the previously proposed hardware accelerator for GMMs. Our proposed design was demonstrated as part of the complete subsystem, allowing for visualization of the constructed map in real-time. The proposed design was demonstrated to perform at 100MHz in isolation and verified for its performance with a 50MHz subsystem on AMD Virtex UltraScale+ VCU118 FPGA.
Date issued
2024-05
URI
https://hdl.handle.net/1721.1/156997
Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Publisher
Massachusetts Institute of Technology

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