Effects of Hardware Design Choices on Neural Network Accuracy in Analog Inference Accelerators

Abstract

Analog accelerators can enable energy-efficient and high-throughput deep neural network (DNN) computations by computing in memory. Unfortunately, device and circuit nonidealities in these accelerators, such as noise and quantization, can also lead to low DNN inference accuracy due to computation errors arising from these non-idealities. These errors are largely a function of both the choice of DNN workload and different hardware design choices, such as circuit topology and DNN operand encoding. Different hardware design choices can affect the energy, throughput, and area of the system, so it is important to understand how these design choices interact with DNN inference accuracy. However, there is a lack of a systemic understanding of how each of these hardware design decisions affects accuracy and how they interact with other design decisions. To address these issues, we model how hardware design choices can lead to analog errors such as noise and quantization. Then, we explore these errors affect inference accuracy in analog accelerators and how tradeoffs can be made between inference accuracy, energy efficiency, area, and throughput. We find that analog errors generated from hardware design decisions can generate different amounts of accuracy loss depending on which layer in a DNN is subject to these analog errors. This leads to the structure of the DNN having a significant impact in how hardware design choices affect DNN inference accuracy, especially with respect to the individual layers of a DNN. We use knowledge of the relationships between device and circuit non-idealities to improve the accuracy of published analog accelerators and analyze the energy and area costs of the increased accuracy.