Predictive multiple sampling algorithm with overlapping integration intervals for linear wide dynamic range integrating image sensors

Abstract

Machine vision systems are used in a wide range of applications such as security, automated quality control and intelligent transportation systems. Several of these systems need to extract information from natural scenes in the section of the electromagnetic spectrum visible to humans. These scenes can easily have intra-frame illumination ratios in excess of 10⁶ : 1. Solid-state image sensors that can correctly process wide illumination dynamic range scenes are therefore required to ensure correct reliability and performance. This thesis describes a new algorithm to linearly increase the illumination dynamic range of integrating-type image sensors. A user-defined integration time is taken as a reference to create a potentially large set of integration intervals of different duration (the selected integration time being the longest) but with a common end. The light intensity received by each pixel in the sensing array is used to choose the optimal integration interval from the set, while a pixel saturation predictive decision is used to overlap the integration intervals within the given integration time such that only one frame using the optimal integration interval for each pixel is produced. The total integration time is never exceeded. Benefits from this approach are motion minimization, real-time operation, reduced memory requirements, programmable light intensity dynamic range increase and access to incremental light intensity information during the integration time.

(cont.) The algorithm is fully described with special attention to the resulting sensor transfer function, the signal-to-noise ratio, characterization of types and effects of errors in the predictive decision, calculation of the optimal integration intervals set given a certain set size, calculation of the optimal number of integration intervals, and impact of the new algorithm to image data compression. An efficient mapping of this algorithm to a CMOS process was done by designing a proof-of-concept integrated circuit in a 0.18[mu]m 1.8V 5-metal layer process. The major components of the chip are a 1/3" VGA (640 x 480) pixel array, a 4bit per pixel memory array, an integration controller array and an analog-to-digital converter/correlated double sampled (ADC/CDS) array. Supporting components include pixel and memory row decoders, memory and converter output digital multiplexers, pixel-to-ADC/CDS analog multiplexer and test structures. The pixels have a fill factor of nearly 50%, as most of the needed system additions and complexity were taken off-pixel. The prototype is fully functional and linearly expands the dynamic range by more than 60dB.