A PCI Express to PCIX Bridge optimized for performance and area

Abstract

This thesis project involves the architecture, implementation, and verification of a high bandwidth, low cost ASIC digital logic core that is compliant with the PCI Express to PCIX Bridge Specification. The core supports PCI Express and PCIX transactions, x16 PCI Express link widths, 32 and 64-bit PCIX link widths, all PCI Express and PCIX packet sizes, transaction ordering and queuing, relaxed ordering, flow control, and buffer management. Performance and area are optimized at the architectural and logic levels. The core is approximately 27K gate count, runs at a maximum of 250 MHz, and is synthesized to a current standard technology. This thesis explores PCI Express, PCIX, and PCI technologies, architectural design, development of Verilog and Vera models, thorough module-level verification, the development of a PCI Express/PCIX system verification environment, synthesis, static timing analysis, and performance and area evaluations. The work has been completed in IBM Microelectronics in Burlington, Vermont as part of the MIT VI-A Program.