Wafer bonding : mechanics-based models and experiments

Abstract

Direct wafer bonding has emerged as an important technology in the manufacture of silicon-on-insulator substrates (SOI), microelectromechanical systems (MEMS), and three-dimensional integrated circuits (3D IC's). While the process is currently employed in applications such as these, a lack of knowledge of the basic mechanics of the process has made developing robust processes and preventing process failures extremely challenging. The current work addresses this problem through the development and validation of mechanics-based models that connect the wafer geometry, etch pattern, clamping configuration, and work of adhesion to bonding failure. An energy-based bonding criterion, which allows the effect of flatness variations and etch patterns to be quantified, is presented and employed to develop analytical and numerical models. Analytical models, based on plate theory, are developed to examine the role of wafer-scale shape variations, etch patterns, and the clamping configuration. Finite element models are developed to verify the analytical models and to evaluate the bonding criterion for wafers with anisotropic elastic properties and arbitrary geometries. Experiments in which silicon substrates with wafer-scale shape variations and etch patterns were bonded demonstrate that the shape and size of the bonded area and the shape of the bonded pair can be predicted using the models developed. The effect of mid-spatial wavelength height variations (nanotopography) on bonding is examined through a combination of modeling and experiments. The experiments and analysis provide a route for characterizing nanotopography and assessing its impact on bonding. The accuracy of the wafer bonded double cantilever beam, which

(cont.) is one method to evaluate the key process parameter of interface toughness, is also examined in the current work. The results of the modeling and experiments are discussed to provide guidance in process, device, and tool design. The models that are presented may be used to establish tolerances on wafer geometry and to improve process control.