WSIM configurable digital signal processor simulator/debugger

Abstract

This M.Eng. Thesis presents a design and implementation of a full-featured configurable Digital Signal Processor (DSP) simulator/debugger. The user will be able to set configurations in order to model a specific architecture design. The simulator will have a command interpreter to listen to and process commands given by the user. When supplied with an assembly program, the simulator will allow the user to step through the execution of the program cycle by cycle, as well as calculate statistics like instruction, resource, and cache profiling. Some of the main features of the simulator are a multiply-accumulate unit, memory with direct and indirect offset addressing, and loop instructions.