Application of three-dimensional circuit integration to global clock distribution

Abstract

As the semi-conductor industry moves towards deep sub-micron designs, efficiency of chip-wide communication is becoming the limiting factor on system performance. One globally distributed signal with significant effect on system performance is the clock signal. In this paper utilization of three-dimensional circuit integration to reduce the negative effects of technology scaling on clock signal distribution is investigated. A design is proposed that removes the clock distribution network from the same active plane as the logical functions of the system and places them on a separate, but electrically connected active plane. Proposed benefits of a three-dimensional distribution network are the reduction of global skew, greater signal integrity, and an increase in system density. All aspects of the design process are detailed including methodology, simulation tools and verification, interconnect and repeater design, the three-dimensional integration process, and the overall predicted system benefits.