dc.contributor.advisor | Anant Agarwal and Umar Saif. | en_US |
dc.contributor.author | Anderson, James William, 1981- | en_US |
dc.contributor.other | Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. | en_US |
dc.date.accessioned | 2005-06-02T19:15:10Z | |
dc.date.available | 2005-06-02T19:15:10Z | |
dc.date.copyright | 2004 | en_US |
dc.date.issued | 2004 | en_US |
dc.identifier.uri | http://hdl.handle.net/1721.1/17936 | |
dc.description | Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004. | en_US |
dc.description | Includes bibliographical references (p. 59-60). | en_US |
dc.description.abstract | Conventionally, high-speed routers are built using custom hardware, typically dubbed as network processors. A prominent example of such a network processor is the Intel IXP1200. Such a network processor typically takes years of effort in the design, fabrication and refinement of the custom hardware, and, worst, must be frequently redesigned to meet the oft-changing requirements of emerging network applications. This thesis presents the design and implementation of a software gigabit network router on a general-purpose microprocessor using MIT's Raw microprocessor. The Raw processor, developed by the Computer Architecture Group at MIT, has sixteen RISC processors, arranged as a grid, that communicate through programmable switches and hardware network interconnects with single-cycle latencies. As opposed to previous high-speed network routers, the Raw router is built without using any custom hardware, and achieves its performance by carefully programming and orchestrating, in software, the interconnects within the Raw chip. Our Raw implementation uses stream-oriented abstractions and differs significantly from that of commercial network processors, which use memory-oriented semantics. Consequently, the Raw router is not only flexible in its architecture and easy to upgrade, our results show that the Raw Router is more than three times faster than a router built using Intel's custom-made IXP1200 network processor. | en_US |
dc.description.statementofresponsibility | by James William Anderson. | en_US |
dc.format.extent | 60 p. | en_US |
dc.format.extent | 2291026 bytes | |
dc.format.extent | 2290832 bytes | |
dc.format.mimetype | application/pdf | |
dc.format.mimetype | application/pdf | |
dc.language.iso | eng | en_US |
dc.publisher | Massachusetts Institute of Technology | en_US |
dc.rights | M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. | en_US |
dc.rights.uri | http://dspace.mit.edu/handle/1721.1/7582 | |
dc.subject | Electrical Engineering and Computer Science. | en_US |
dc.title | The raw router : gigabit routing on a general-purpose microprocessor | en_US |
dc.title.alternative | raw router : an analysis and evaluation of a parallel routing architecture | en_US |
dc.type | Thesis | en_US |
dc.description.degree | M.Eng. | en_US |
dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | |
dc.identifier.oclc | 56821591 | en_US |