The SCALE DRAM subsystem

Abstract

Dynamic Random Access Memory (DRAM) is consuming an ever-increasing portion of a system's energy budget as advances are made in low-power processors. In order to reduce these energy costs, modern DRAM chips implement low-power operating modes that significantly reduce energy consumption but introduce a performance penalty. This thesis discusses the design and evaluation of an energy-aware DRAM subsystem which leverages the power-saving features of modern DRAM chips while maintaining acceptable system performance. As this subsystem may employ a number of different system policies, the effect of each of these policies on system energy and performance is evaluated. The optimal overall policy configurations in terms of energy, delay, and energy-delay product are presented and evaluated. The configuration which minimizes the energy-delay product demonstrates average energy savings of 41.8% as compared to the high-performance configuration, while only introducing an 8.8% performance degradation.