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dc.contributor.advisorAkintunde Akinwande and Ioannis Kymissis.en_US
dc.contributor.authorWang, Annie I. (Annie I-Jen), 1981-en_US
dc.contributor.otherMassachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.en_US
dc.date.accessioned2005-06-02T19:34:01Z
dc.date.available2005-06-02T19:34:01Z
dc.date.copyright2004en_US
dc.date.issued2004en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/17998
dc.descriptionThesis (M. Eng. and S.B.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.en_US
dc.descriptionIncludes bibliographical references (p. 59-63).en_US
dc.description.abstractOrganic field effect transistors (OFETs) offer a suitable building block for many flexible, large-area applications such as display backplanes, electronic textiles, and robotic skin. Besides the organic semiconductor itself, an important area in the development of OFETs is the gate dielectric material. In this thesis the organic polymer parylene is studied as a gate dielectric for pentacene OFETs. The three main areas of study were: (1) parylene's performance as a dielectric, (2) possible improvement of OFETs by surface treatments, and (3) the effects of interface traps on threshold voltage and parasitic bulk conductivity. Parylene was found to provide a favorable, hydrophobic interface for pentacene growth, yielding transistors with mobilities > 0.5cm²/Vs at -100V. While the two surface treatments explored did increase contact angle by 10-20⁰, neither the ammonium sulfide nor the polystyrene treatment significantly improved pentacene packing or mobility. Modification of the parylene surface using an oxygen plasma introduced traps at the semiconductor-dielectric interface, observable through a variety of characterization techniques. A model is developed to explain how the fixed and mobile charges these traps introduce influence the threshold voltage and parasitic conductivity in the device.en_US
dc.description.statementofresponsibilityby Annie I. Wang.en_US
dc.format.extent63 p.en_US
dc.format.extent2693265 bytes
dc.format.extent2699280 bytes
dc.format.mimetypeapplication/pdf
dc.format.mimetypeapplication/pdf
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsM.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582
dc.subjectElectrical Engineering and Computer Science.en_US
dc.titleThreshold voltage in pentacene field effect transistors with parylene dielectricen_US
dc.typeThesisen_US
dc.description.degreeM.Eng.and S.B.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
dc.identifier.oclc57196449en_US


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