Cell-based array for deep sub-micron technologies

Author(s)
Oey, James Boe-Kian, 1980-
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Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Advisor
Christopher J. Terman.
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Abstract
In this thesis I explore transistor topologies for high density cell-based arrays that allows for dense computation blocks, small memory cells, and strong signal drivers. This involves simulating different circuit types with HSPICE to determine ideal transistor sizes. Using Magic and the results of the HSPICE simulations, I explore transistor topologies with different ratios of nFets to pFets. An analysis on the technology shows important characteristics for digital systems and how they relate to the explored transistor topologies.
Description
Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2003.
 
Includes bibliographical references (p. 161).
 
Date issued
2003
URI
http://hdl.handle.net/1721.1/18030
Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Publisher
Massachusetts Institute of Technology
Keywords
Electrical Engineering and Computer Science.
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