Hot-carrier reliability of MOSFETs at room and cryogenic temperature

Abstract

Hot-carrier reliability is an increasingly important issue as the geometry scaling of MOSFET continues down to the sub-quarter micron regime. The power-supply voltage does not scale at the same rate as the device dimensions, and thus, the peak lateral E-field in the channel increases. Hot-carriers, generated by this high lateral E-field, gain more kinetic energy and cause damage to the device as the geometry dimension of MOSFETs shortens. In order to model the device hot-carrier degradation accurately, accurate model parameter extraction is critically important. This thesis discusses the model parameters' dependence on the stress conditions and its implications in terms of the device lifetime prediction procedure. As geometry scaling approaches the physical limit of fabrication techniques, such as photolithography, temperature scaling becomes a more viable alternative. MOSFET performance enhancement has been investigated and verified at cryogenic temperatures, such as at 77K. However, hot-carrier reliability problems have been shown to be exacerbated at low temperature. As the mean-free path increases at low temperature due to reduced phonon-scattering, hot-carriers become more energetic at low temperature, causing more device degradation. It is clear that various hot-carrier reliability issues must be clearly understood in order to optimize the device performance vs. reliability trade-off, both at short channel lengths and low temperatures. This thesis resolves numerous, unresolved issues of hot-carrier reliability at both room and cryogenic temperature, and develops a general framework for hot carrier reliability assessment.