Allocating decoupling capacitors to reduce simultaneous switching noise on chips

Abstract

L dI/dt noise due to simultaneous switching of circuits on chips is a growing problem in VLSI design. This kind of noise can lead to timing errors and significant circuit slowdowns, if not kept within reasonable bounds. The most common way of reducing this form of noise is the addition of decoupling capacitance on chip. However, adding decoupling capacitance can take significant area and can make routing very difficult. The goals of this thesis are twofold: first, to characterize the relationship between noise propagation on chip and parameters such as on-chip resistance and capacitance; and second, to develop an algorithm which will minimize the number of decoupling capacitors on chip while simultaneously reducing the noise to within acceptable boundaries.