Pattern-placement-error detection for spatial-phase-locked e-beam lithography (SPLEBL)

Abstract

Spatial-phase-locked electron-beam lithography (SPLEBL) is a new paradigm for scanning electron-beam lithography (SEBL) that permits nanometer-level pattern placement accuracy. Unlike conventional SEBL systems which run in an open-loop fashion, SPLEBL uses continuous feedback to directly monitor and correct the beam's position, eliminating the need for expensive shielding equipment and costly isolation techniques. When compared to the most advanced and sophisticated SEBL systems, SPLEBL exceeds all of them in the areas of pattern-placement accuracy and affordability. However, much improvement is needed to increase the throughput of SPLEBL to a level on par with its commercial counterparts. As SPLEBL is further optimized for throughput and affordability, the placement-error detection and correction subsystem will need to be upgraded with a custom hardware solution. The work presented in this thesis describes the design of an efficient error detection and correction mechanism for SPLEBL and how it could be implemented as a digital circuit. An error-detection algorithm, well suited for digital hardware, has been developed and characterized. A digital circuit design to implement the algorithm has been created, optimized, and verified using the MathWorks SimulinkTM and the Xilinx System GeneratorTM hardware design tools.