Fundamental building blocks for a compact optoelectronic neural network processor

Abstract

The focus of this thesis is interconnects within the Compact Optoelectronic Neural Network Processor. The goal of the Compact Optoelectronic Neural Network Processor Project (CONNPP) is to build a small, rugged neural network co-processing unit. This processor will be optimized for solving various signal processing problems such as image segmentation or facial recognition. These represent a class of problems for which the traditional logic-based architectures are not optimized. The CONNPP utilizes the processing power of traditional electronic integrated circuits along with the communications benefits of optoelectronic interconnects to provide a three-dimensionally scalable architecture. The topic of interconnects includes both optoelectronic interconnects between processing planes as well as wire based interconnects within the processing planes. The optoelectronic inter-plane interconnects allow the CONNPP to achieve 3-dimensional scalablility. These interconnects employ an array of holograms designed and fabricated using an analytic model that has been developed. This analytic model takes into account reading and writing the hologram at different wavelengths as well as non-idealities of the optoelectronic devices being used. The analytic model was tested and showed agreement with experiment to within 10% of the calculated values. The photodetectors used for the testing of this system have been designed within standard process technologies using a lateral PiN structure and a novel lateral BJT structure. In addition, highly-linear transimpedance amplifiers were designed to condition the signal from the photodetector for further processing.

(cont.) Finally, a new chip-level interconnect architecture has been proposed for the CONNPP that utilizes a system bus to provide global connectivity between the neurons within the plane of the chip. Software models were built to simulate various chip-level connectivity schemes. These simulations show the significant potential benefits of the global bus-based chip-level architecture that has been proposed.