Engineered substrates for coplanar integration of lattice-mismatched semiconductors with silicon

Abstract

As we approach the end of traditional CMOS scaling, further improvements in integrated circuit performance and functionality will become limited by the inherently low carrier mobility and indirect bandgap of silicon. These performance shortcomings can be supplemented with high performance semiconductors such as Ge and GaAs, which have respectively improved carrier mobilities and a direct bandgap for efficient light emission. However, due to the economic superiority of Si-based microelectronics, it is unlikely that the CMOS industry will abandon Si entirely. Instead, it will be necessary to integrate materials such as Ge and GaAs with the Si platform by means of engineered substrates. In this thesis, thin Ge layers were transferred to Si by wafer bonding of compositionally graded structures. This approach combines the beneficial aspects of graded buffers with those of wafer bonding to provide a coplanar integration platform for lattice-mismatched semiconductors. The various innovations that were necessary to realize epitaxial layer transfer from virtual substrates stem from the fact that thin films of Ge are difficult to planarize. The large surface roughness of graded buffers requires smoothing of the surface prior to bonding. The poor surface passivation of GeO2 in aqueous chemo-mechanical planarization (CMP) slurries necessitates that Ge virtual substrates be planarized indirectly, using a deposited CMP layer. Furthermore, H-induced exfoliation is the only practical method of separating a thin Ge layer from the surface of a virtual substrate, leading to extensive surface damage of the transferred layer.

(cont.) This damage is traditionally removed using a CMP step for exfoliated Si layers. However for Ge transfer, a Sio.4Geo.6 etch-stop layer was incorporated for damage removal using a selective chemical etch. These techniques have enabled transferal of epitaxial Ge-on-insulator (GOI) structures to large diameter Si wafers. Tensilely strained layers have the ability to attract interstitially-dissolved hydrogen and accelerate the nucleation of platelets- both of which contribute to the layer exfoliation process. As a result, a strained Sio.4Geo.6 layer was used to enhance the exfoliation kinetics of Ge by providing a gettering site for ion-implanted hydrogen. During 250 C annealing of hydrogen-implanted Si0.4Ge.6/Ge gettering structures, preferentially-nucleated platelets are made to grow within the Sio.4Ge.6 layer with minimal loss of hydrogen to surface effusion. Subsequent annealing at a temperature exceeding >300 C yields significantly improved surface blistering kinetics over samples which do not contain a gettering layer. A platelet growth model was formulated accounting for both chemical and strain energy contributions to the free energy of platelet formation. Microstructure and strain relaxation data corroborate the free energy computations, revealing two kinetically- limited regimes of platelet growth within tensilely strained Sio.4Geo.6 layers. Low temperature annealing allows the platelets to grow in the strain-limited regime, resulting in a local platelet density of >1010 cm-2 and significantly improved exfoliation kinetics. Incorporation of strained layers has the potential of reducing the implantation dose necessary for layer transfer. Combined with virtual substrate bonding, gettering structures provide a promising solution for economical integration of high performance materials with silicon.