| dc.contributor.advisor | Srinivas Devadas. | en_US |
| dc.contributor.author | Croswell, Joseph Adam, 1977- | en_US |
| dc.contributor.other | Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. | en_US |
| dc.date.accessioned | 2006-03-28T19:50:54Z | |
| dc.date.available | 2006-03-28T19:50:54Z | |
| dc.date.copyright | 2000 | en_US |
| dc.date.issued | 2000 | en_US |
| dc.identifier.uri | http://hdl.handle.net/1721.1/32094 | |
| dc.description | Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2000. | en_US |
| dc.description | This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections. | en_US |
| dc.description | Includes bibliographical references (leaf 57). | en_US |
| dc.description.abstract | Manufacturing a DRAM module that is error free is a very difficult process. This process is becoming more difficult when only utilizing the current methods for producing an error free DRAM. Error correction codes (ECCs) and cell replacement are two methods currently used in isolation of each other in order to solve two of the problems with this manufacturing process: increasing reliability and increasing yield, respectively. Possible solutions to this problem are proposed and evaluated qualitatively in discussion. Also, a simulation model is produced in order to simulate the impacts of various strategies in order to evaluate their effectiveness. | en_US |
| dc.description.statementofresponsibility | by Joseph Adam Croswell. | en_US |
| dc.format.extent | 57 leaves | en_US |
| dc.format.extent | 250474 bytes | |
| dc.format.extent | 249930 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.format.mimetype | application/pdf | |
| dc.language.iso | eng | en_US |
| dc.publisher | Massachusetts Institute of Technology | en_US |
| dc.rights | M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. | en_US |
| dc.rights.uri | http://dspace.mit.edu/handle/1721.1/7582 | |
| dc.subject | Electrical Engineering and Computer Science. | en_US |
| dc.title | A model for analysis of the effects of redundancy and error correction on DRAM memory yield and reliability | en_US |
| dc.type | Thesis | en_US |
| dc.description.degree | M.Eng. | en_US |
| dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | |
| dc.identifier.oclc | 48981811 | en_US |
