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dc.contributor.advisorFrédo Durand.en_US
dc.contributor.authorChen, Jiawen (Jiawen Kevin)en_US
dc.contributor.otherMassachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.en_US
dc.date.accessioned2006-06-19T17:42:00Z
dc.date.available2006-06-19T17:42:00Z
dc.date.copyright2005en_US
dc.date.issued2005en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/33115
dc.descriptionThesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.en_US
dc.descriptionIncludes bibliographical references (p. 77-80).en_US
dc.description.abstractCommodity graphics hardware has become increasingly programmable over the last few years, but has been limited to a fixed resource allocation. These architectures handle some workloads well, others poorly; load-balancing to maximize graphics hardware performance has become a critical issue. I have designed a system that solves the load-balancing problem in real-time graphics by using compile-time resource allocation on general-purpose hardware. I implemented a flexible graphics pipeline on Raw, a tile-based multicore processor. The complete graphics pipeline is expressed using StreamIt, a high-level language based on the stream programming model. The StreamIt compiler automatically maps the stream computation onto the Raw architecture. The system is evaluated by comparing the performance of the flexible pipeline with a fixed allocation representative of commodity hardware on common rendering tasks. The benchmarks place workloads on different parts of the pipeline to determine the effectiveness of the load-balance. The flexible pipeline achieves up to twice the throughput of a static allocation.en_US
dc.description.statementofresponsibilityby Jiawen Chen.en_US
dc.format.extent80 p.en_US
dc.format.extent3159538 bytes
dc.format.extent3163126 bytes
dc.format.mimetypeapplication/pdf
dc.format.mimetypeapplication/pdf
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsM.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582
dc.subjectElectrical Engineering and Computer Science.en_US
dc.titleLoad-balanced rendering on a general-purpose tiled architectureen_US
dc.typeThesisen_US
dc.description.degreeM.Eng.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
dc.identifier.oclc62233328en_US


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