Lower power RF transceiver modeling and design for wireless microsensor networks

Abstract

The design of wireless microsensor systems has gained increasing importance for a variety of civil and military applications. With the objective of providing short-range connectivity with significant fault tolerance, these systems find usage in such diverse areas as environmental monitoring, industrial process automation, and field surveillance. The main design objective is to, maximize the battery life of the sensor nodes while ensuring reliable operations. To achieve this goal, the microsensor node has to be designed in a highly integrated fashion and optimized across all levels of system abstraction. For microsensor networks, the RF transceiver dominates the power consumption. The concept of transceiver power efficiency is introduced, which defines the ratio of RF transmit power to transceiver electronics power, to show that short-range RF transceivers have low transceiver power efficiency. A system energy model is developed to show that the battery life of the transceiver not only depends on its power consumption, but more importantly, on its energy dissipation over the operation cycle.

(cont.) Both the transceiver power efficiency and the battery life can be improved significantly by increasing the data rate, reducing the start-up time, and improving the PA efficiency. Increasing the data rate drives down the fixed energy cost of the transceiver. Reducing the start-up time decreases the start-up energy overhead. Improving the PA efficiency lowers the energy per bit cost of the power amplifier. The voltage controlled oscillator occupies a large fraction of the total energy budget in the operation of the microsensor transceiver. The design of integrated LC oscillators is investigated on both the system and the circuit design levels. On the system level, the phase noise requirement of the VCO as a function of the channel bandwidth and the data rate is derived. On the circuit level, the physical mechanisms of phase noise are examined and a low-power 5-GHz VCO is designed and fabricated in a 0.18-[mu]m SiGe BiCMOS process. A technique is proposed to trade off phase noise for a lower bias current through the sizing of the switching transistors. This VCO demonstrates a phase noise of -125dBc/Hz at 7mA core bias current and -llOdBc/Hz at 1.5mA, which exceeds the system phase noise requirement.