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A CMOS-compatible compact display

Author(s)
Chen, Andrew R. (Andrew Raymond)
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Alternative title
Complementary metal oxide semiconductor-compatible compact display
Other Contributors
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Advisor
Hae-Seung Lee and Akintunde I. Akinwande.
Terms of use
M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. http://dspace.mit.edu/handle/1721.1/33934 http://dspace.mit.edu/handle/1721.1/7582
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Abstract
Portable information devices demand displays with high resolution and high image quality that are increasingly compact and energy-efficient. Microdisplays consisting of a silicon CMOS backplane integrated with light generating or modifying devices, are being developed for direct-view and projection applications. A microdisplay architecture using silicon light emitters and image intensification suitable for a micro-projector application is developed. A standard low-voltage CMOS IC incorporating display drivers and an array of avalanche diodes produces a faint optical image, and an image intensifier efficiently amplifies the image to useful brightness. This architecture has high efficiency and the potential to achieve adequate luminance for projection applications. A proof-of-concept system with 16x32 arrays is implemented and evaluated. A high-performance silicon backplane for the above system is designed, implemented, and evaluated. The backplane is a standard CMOS die including a 360x200 pixel array with silicon light emitters, and 10b precision current-mode driver circuits. The driver circuits can support a number of emissive display technologies including silicon light emitters and organic light emitting diode (OLED).
 
(cont.) They employ a self-calibration technique based on the current copier circuit to minimize variation and fixed-pattern noise while reducing circuit area by a factor of five to seven compared to a conventional solution. A circuit technique to improve the retention time of dynamic analog memories is also presented. This technique allows a dynamic analog memory to retain 10b precision for 500ms at room temperature.
 
Description
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2005.
 
Includes bibliographical references (p. 119-127).
 
Date issued
2005
URI
http://dspace.mit.edu/handle/1721.1/33934
http://hdl.handle.net/1721.1/33934
Department
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Publisher
Massachusetts Institute of Technology
Keywords
Electrical Engineering and Computer Science.

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  • Electrical Engineering and Computer Sciences - Ph.D. / Sc.D.
  • Electrical Engineering and Computer Sciences - Ph.D. / Sc.D.

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