Design for manufacturability with regular fabrics in digital integrated circuits

Abstract

Integrated circuit design is limited by manufacturability. As devices scale down, sensitivity to process variation increases dramatically, making design for manufacturability a critical concern. Designers must identify the designs that generate the least systematic process variation, e.g., from pattern dependent effects, but must also build circuits that are robust to the remaining process or environmental random variations. This research addresses both ideas, by examining integrated circuit design styles and aspects that can help curb process variation and improve manufacturability and performance in future technology generations. One suggested method to reduce variation sensitivity in system designs has been the concept of design regularity. Long used in FPGAs, and SRAMs, the concept of repeatable blocks is examined in this work as a method of reducing circuit variation. Layout based variation is examined in three designs with different distinctions of regularity: a Via-Patterned Gate Array (VPGA) FPU, a Berkeley BEE-generated decoder, and a low power FPGA. The circuit level impact on variation is also considered, by examining several circuit architectures. This includes analysis of the novel Limited Switch Dynamic Logic (LSDL) style, which reduces design area and encourages regularity through minimum logic sizing.

(cont.) Robustness to spatial variation and slanted plane effects is examined with a common-centroid based layout methodology for digital integrated circuits. Finally, a methodology is introduced in the form of the Monte Carlo Variation Analysis Engine whereby distributed process variables are fed into repeated simulation runs, output metrics are recorded, and regressions are measured to expose design sensitivities. The results for different layout and circuit design styles identify improvements that may be made to improve robustness to variation. We show that design regularity is a significant factor in mitigating sensitivity to process variation and is worthy of further examination.