Development of an architectural design tool for 3-D VLSI sensors

Abstract

Three dimensional integration schemes for VLSI have the potential for enabling the development of new high-performance architectures for applications such as focal plane sensors. Due to the high costs involved in 3-D VLSI fabrication and the fabrication complexity of 3-D integration, analysis of the design and process tradeoffs for a particular application is essential. An architectural and topological design tool is presented that enables the high-level analysis and optimization of sensor architectures targeted to a variety of 3-D VLSI process options. This design tool is based on an inference chain evaluation framework, and allows for a high-level structural representation of a circuit architecture to be considered in conjunction with low-level process models. Approximation strategies for projecting circuit area and performance are incorporated into the inference chain relations.