| dc.contributor.advisor | Jonathan Allen. | en_US |
| dc.contributor.author | Tan, Chin Hwee | en_US |
| dc.date.accessioned | 2007-02-21T10:31:41Z | |
| dc.date.available | 2007-02-21T10:31:41Z | |
| dc.date.copyright | 1994 | en_US |
| dc.date.issued | 1994 | en_US |
| dc.identifier.uri | http://hdl.handle.net/1721.1/35979 | |
| dc.description | Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994. | en_US |
| dc.description | Includes bibliographical references (p. 85-88). | en_US |
| dc.description.statementofresponsibility | by Chin Hwee Tan. | en_US |
| dc.format.extent | 88 p. | en_US |
| dc.language.iso | eng | en_US |
| dc.publisher | Massachusetts Institute of Technology | en_US |
| dc.rights | M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission. | en_US |
| dc.rights.uri | http://dspace.mit.edu/handle/1721.1/7582 | |
| dc.subject | Electrical Engineering and Computer Science | en_US |
| dc.title | Optimization of power and delay in VLSI circuits using transistor sizing and input ordering | en_US |
| dc.type | Thesis | en_US |
| dc.description.degree | M.S. | en_US |
| dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | |
| dc.identifier.oclc | 31363694 | en_US |
