Substrate and channel engineering for improving performance of strained-SiGe MOSFETs

Abstract

With VLSI technology moving closer towards fundamental physical limits, a way to further improve the transistor drive current for superior circuit performance is enhancing the average velocity of carriers in the channel. In order to enable technology boosters like strained channels on the commercially developed Si platform, a low threading dislocation density SiGe platform is required. A relaxed SilGe. graded buffer creates a larger lattice constant on a Si substrate while providing low threading dislocation densities (TDD) on the order of 105 cm-2. For many III-V devices on Si, such as high-efficiency multi-junction solar cells, the SiGe graded buffer approach is hindered somewhat by the fact that relatively thick buffers must be grown to relieve the strain effectively. A way to reduce the thickness of SiGe graded buffer is to use larger mismatch (10% Ge difference) at each step. Growing a larger mismatch layer at high temperature leads to a higher threading dislocation density (TDD). In this work, the rate of plastic strain relaxation in a mismatched layer and misfit dislocation distribution in the layer are identified to be important parameters which affect the TDD in a mismatched SiGe layer.

(cont.) Reducing the TDD in a mismatched SiGe layer on Si requires slow plastic strain relaxation which can be achieved by growing layers at slower growth rates. Using lower growth temperatures to reduce the growth rates, however, leads to a poorly relaxed layer. A Time-Temperature-Threading Dislocation Density diagram has been developed in this work and explains that a high temperature anneal for relaxing the layer leads to undesirable TDD escalation. A gradual increase in the anneal temperature results in slow plastic relaxation leading to a reduced TDD. The remaining elastic strain can be completely removed by using strain relieving layer on top. Repetition of this minimized 10% mismatched layer achieves high Ge lattice constant in less than half the thickness of a conventional graded buffer. Using the conventional SiGe relaxed buffers, strained layer heterostructures which provide enhanced hole and electron mobilities can be fabricated. A dual channel heterostructure consisting of strained-Si (-Si) / strained-Sil yGey (-Sil.yGey) on a relaxed SilxGex buffer (y>x), provides a platform for fabricating MOSFETs with high hole mobility (peff). The impressive hole ff enhancements obtained on dual channel heterostructures depend greatly on the Ge concentration and the strain' in the -Sil.yGey layer.

(cont.) Ge out-diffusion during high temperature processing steps from the c-Sil yGey layer into the relaxed SilxGex buffer reduces the Ge concentration and the strain in the layer leading to reduced hole peff in these heterostructures2. For estimating the thermal budgets of the strained layer heterostructures, a diffusion coefficient for Ge in crystalline SiGe has been formulated. We have also implemented a novel, more accurate finite difference scheme for estimating thermal budgets of strained SiGe heterostructure with steeply varying concentrations. It is found that due to the very small diffusivity of Ge in Si, the out-diffusion of Ge occurs primarily from the e-SilyGey layer into the relaxed Sil.Gex buffer with much less diffusion into the S-Si3. This motivated the inclusion of a s-Si layer between the e-SilyGey and relaxed Sil. xGex buffer for reducing the Ge out-flux. The resulting heterostructure is referred to as tri-layer heterostructure4. Based on our numerical investigations and annealing experiments regimes in temperature and concentration where the tri-layer is expected to be thermally more stable as compared to corresponding dual channels have been outlined.

(cont.) Hole pleff enhancements are retained to a much higher extent in a tri-layer heterostructure after high temperature processing as compared to a dual channel heterostructure. Improved hole mobilities in this heterostructure are also observed over similar dual channel heterostructures. The improved thermal stability and hole lef of a tri-layer heterostructure makes it an ideal platform for fabricating high peff MOSFETs that can be processed over higher temperatures without significant losses in hole ,uef.