Global partitioning of parallel loops and data arrays for caches and distributed memory in multiprocessors

Author(s)
Barua, Rajeev K. (Rajeev Kumar)
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Advisor
A. Agarwal.
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Description
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.
 
Includes bibliographical references (p. 49-50).
 
Date issued
1994
URI
http://hdl.handle.net/1721.1/36455
Department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Publisher
Massachusetts Institute of Technology
Keywords
Electrical Engineering and Computer Science
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