Characterization and modeling of plasma etch pattern dependencies in integrated circuits

Abstract

A quantitative model capturing pattern dependent effects in plasma etching of integrated circuits (ICs) is presented. Plasma etching is a key process for pattern formation in IC manufacturing. Unfortunately, pattern dependent non-uniformities arise in plasma etching due to microloading and RIE lag. This thesis contributes a semi-empirical methodology for capturing and modeling microloading, RIE lag, and related pattern dependent effects. We apply this methodology to the study of interconnect trench etching, and show that an integrated model is able to predict both pattern density and feature size dependent non-uniformities in trench depth. Previous studies of variation in plasma etching have characterized microloading (due to pattern density), and RIE lag (aspect ratio dependent etching or ARDE) as distinct causes of etch non-uniformity for individual features. In contrast to these previous works, we present here a characterization and computational methodology for predicting IC etch variation on a chip scale that integrates both layout pattern density and feature scale or ARDE dependencies. The proposed integrated model performs well in predicting etch variation as compared to a pattern density only or feature scale only model.