Charge Storage Mechanism and Size Control of Germanium Nanocrystals in a Tri-layer Insulator Structure of a MIS Memory Device

Abstract

A method of synthesizing and controlling the size of germanium nanocrystals is developed. A tri-layer metal-insulator-semiconductor (MIS) memory device structure comprising of a thin (~5nm) silicon dioxide (SiO₂) layer grown using rapid thermal oxidation (RTO), followed by a layer of Ge+SiO₂ of varying thickness (3 - 6 nm) deposited using a radio frequency (rf) co-sputtering technique, and a capping SiO₂ layer (50nm) deposited using rf sputtering is investigated. It was verified that the size of germanium (Ge) nanocrystals in the vertical z-direction in the trilayer memory device was controlled by varying the thickness of the middle (cosputtered Ge+SiO₂) layer. From analyses using transmission electron microscopy and capacitance-voltage measurements, we deduced that both electrons and holes are most likely stored within the nanocrystals in the middle layer of the trilayer structure rather than at the interfaces of the nanocrystals with the oxide matrix.