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dc.contributor.advisorAlvin W. Drake.en_US
dc.contributor.authorMirza, Agha Irtazaen_US
dc.date.accessioned2007-05-16T18:54:32Z
dc.date.available2007-05-16T18:54:32Z
dc.date.copyright1995en_US
dc.date.issued1995en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/37537
dc.descriptionThesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1995.en_US
dc.descriptionIncludes bibliographical references (p. 123-124).en_US
dc.description.statementofresponsibilityby Agha Irtaza Mirza.en_US
dc.format.extent124 p.en_US
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsM.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582
dc.subjectElectrical Engineering and Computer Scienceen_US
dc.titleSpatial yield modeling for semiconductor wafersen_US
dc.typeThesisen_US
dc.description.degreeM.S.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
dc.identifier.oclc33228512en_US


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