Process and design techniques for low loss integrated silicon photonics
Author(s)Sparacin, Daniel Knight
Massachusetts Institute of Technology. Dept. of Materials Science and Engineering.
Lionel C. Kimerling.
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Microprocessors have truly revolutionized the efficiency of the world due to the high-volume and low-cost of complimentary metal oxide semiconductor (CMOS) process technology. However, the traditional scaling methods by which chips improve are soon to end. The continued drive towards smaller circuit elements and dense chip architecture has yielded to power consumption, heat production, and electromagnetic interference (RC-delay) limitations. A logical solution to surmounting this electronic interconnect bottleneck is to utilize photonic interconnects. Photonic interconnects (waveguides) offer high data bandwidths with low signal attenuation and virtually zero heat dissipation. Strategic replacement of RC speed-limited electronic interconnects with photonic interconnects is a logical step to improving data processing performance in future microprocessors. Integration of photonic circuits onto electronic chips also enables sought after networking technologies that have higher complexity and unique functionality. Similar to the integrated microchip, the employment of CMOS technology in the fabrication of integrated photonic chips enables high yield, low cost, and increased performance. Essentially, the development of an integrated CMOS compatible photonic circuit technology is an enabler of improved communication.(cont.) However, there are many challenges in realizing a viable, integrated photonic circuit technology. The constraints associated with fabrication of CMOS compatible, high-index-contrast, planar, thin-film photonic devices add difficulty in realizing the necessary components for a complete photonic circuit. Of these components: light source, waveguide, modulator, splitter, filter, and detector; all are limited in performance and functionality by optical transmission loss. As a result, this thesis has focused on diagnosing and addressing the various loss mechanisms that exist in fabricating CMOS compatible channel waveguides. As the building block of higher order photonic devices, waveguides are useful as diagnostic tools with which one can characterize photonic loss mechanisms. Waveguide test methodologies are developed to accurately diagnose the waveguide loss mechanisms (e.g. bulk absorption and interface roughness-scattering) by analyzing transmission loss (T) as a function of signal wavelength (x), waveguide width (w), waveguide height (h), effective index (neff), number of bends (N), and optical power (P).(cont.) Four high index waveguide materials are investigated: silicon on insulator (SOI), amorphous silicon (a-Si), polycrystalline silicon (poly-Si), and Silicon Nitride. The dominant loss mechanism for each material system is different and as a result, unique process and design techniques are developed for each. For SOI waveguides, the loss is dominated by sidewall roughness. As a result, a novel post-etch wet chemical oxidation smoothing method is developed to reduced sidewall roughness and improve waveguide transmission. The employment of a hybrid waveguide design further reduces SOI waveguide losses to 0.35 dB/cm. For a-Si waveguides, loss is dominated by bulk absorption arising from dangling bonds. Loss reduction is achieved by increasing the H-content in the films, thereby satisfying the dangling bonds and reducing the number of absorption sites. Amorphous silicon bulk losses are reduced from 15.2 ± 2 dB/cm to < 1 dB/cm, representing a tractable path for integrating high index contrast waveguides onto multiple chip levels. For SiN waveguides, N-H bond absorption at %=1510 nm is the dominant loss mechanism. Here the use of low H-content precursors is investigated to reduce the number of N-H bond absorption sites.(cont.) A total of six SiN materials are compared with losses as low as 1.5 dB/cm. Ring resonator devices, comprised of channel waveguides, are also investigated. Ring resonators serve as filters for multiplexing and demultiplexing broadband optical signals, dispersion compensators for accurately controlling phase, lasers, and ultrafast all-optical switches. In realizing these devices a ring trimming method is developed to compensate for non-deterministic pattern transfer errors which limit dimensional precision and preclude the fabrication of identical devices across an entire wafer. In this work, a novel photo-oxidation trimming method, using a UV-sensitive, polysilane top cladding material, is employed. The UV-induced refractive index decrease of polysilane (4%) enables accurate and localized trimming of ring resonators. Ring modulator devices are modeled as well. The employment of integrated SiGe ring modulators that utilize the fast Franz-Keyldish effect is discussed. The design constraints involved in monolithically integrating photonic and electronic components are discussed. In particular, the CMOS process challenges: material limitations, epitaxial compatibilities, thermal-budget imposed process order, and device communication requirements are utilized in arriving at an optimal application specific, electronic-photonic integrated chip (AS-EPIC) architecture.
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2006.Includes bibliographical references (p. 256-260).
DepartmentMassachusetts Institute of Technology. Dept. of Materials Science and Engineering.
Massachusetts Institute of Technology
Materials Science and Engineering.