Multi-layer three-dimensional silicon electronics enabled by wafer bonding

Abstract

Three-dimensional integrated circuits (3-D ICs), in the form of a vertical stack of several interconnected device layers, have many performance, form factor, and integration advantages. The main objective of this work is to develop reliable process technology to enable the fabrication of a vertically interconnected silicon multi-layer stack. Low temperature wafer bonding processes, both copper thermo-compression bonding and silicon dioxide fusion bonding, are studied extensively as key enabling technology. Cu thermo-compression bonding is studied for its feasibility as a permanent bond between active layers in a multi-layer stack. It is found that pre-bonding anneal in forming gas can remove surface oxide on Cu wafers and reduce the oxygen content in the bonded layer. The quality of bonded Cu layer is adversely degraded by the formation of interfacial voids. Void nucleation and growth are studied and counter-measures for void suppression are proposed and implemented. Silicon dioxide wafer bonding, on the other hand, is used as a temporary bond to attach a donor wafer to a handle wafer during donor wafer thinning and subsequent layer transfer. Sufficiently high bond strength is obtained with careful surface preparation and activation prior to bonding.

(cont.) Silicon layer can be stacked either in a "face down" or "face up" orientation. Using a combination of wafer bonding and thinning, double-layer stacks in both orientations are fabricated. By repeating these steps on two "face down" double-layer stacks, a four-layer stack is successful demonstrated. A vertically interconnected active layers stack is demonstrated by fabricating poly-silicon resistor chains. Poly-silicon resistors in two layers are electrically connected with interlayer vias. Temperature measurement of metal lines suggests that Cu bonding medium can remove heat from top active layer of a double-layer stack more effectively than oxide bonding medium. Thermal stress induced in a multi-layer stack can pose a serious reliability concern. Analytical and numerical evaluation of thin film stresses of a multi-layer stack is performed. Stresses of interest include normal stress in thin films, and shear and peel stresses at the interfaces. It is found that the Cu bonding layer is under substantial tensile stress that increases with bonding temperature. High stress level in the Cu bonding layer provides a strong driving force for the formation of interfacial voids.