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dc.contributor.advisorAnantha P. Chandrakasan.en_US
dc.contributor.authorHonoré, Francisen_US
dc.contributor.otherMassachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.en_US
dc.date.accessioned2007-07-18T13:08:43Z
dc.date.available2007-07-18T13:08:43Z
dc.date.copyright2006en_US
dc.date.issued2006en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/37911
dc.descriptionThesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.en_US
dc.descriptionIncludes bibliographical references (p. 113-117).en_US
dc.description.abstractField Programmable Gate Arrays (FPGAs) are a class of hardware reconfigurable logic devices based on look-up tables (LUTs) and programmable interconnect that have found broad acceptance for a wide range of applications. However, power consumption is one of the leading obstacles to broader adoption of FPGAs in energy-constrained applications. This thesis addresses active power consumption in FPGAs through the introduction of fine grain configurable power domains. By introducing fine grain power controls, sections of the design that have excess timing margins are able to run at reduced voltage thereby saving power. Delay critical sections can continue to operate at full voltage to maintain the overall performance of the design. A design flow was developed for the analysis and implementation of these configurable power domains. A test chip using dual core voltages fabricated in a 0.18 /m CMOS process features these power reduction techniques. The test chip includes an 8x8 array of logic tiles and a 9x9 switch matrix grid. The chip design flow utilizes a mix of synthesized logic and custom cells. 'The layout required a customized approach to overcome some of the challenges of implementing a fine granularity multiple voltage design.en_US
dc.description.abstract(cont.) A set of benchmark circuits shows a measured average energy-delay improvement of nearly 2X. Additionally, enhancements for the implementation of finite impulse response filters provide a 2.5x improvement in the energy-delay product relative to standard FPGA architectures. This thesis also addresses static: power consumption by reducing sub-threshold leakage through the use of distributed multi-threshold CMOS. A separate test chip using a 0.13 m dual VT process demonstrates the advantages of distributed power gating for sub-threshold leakage reduction by achieving over 10X reduction in static power.en_US
dc.description.statementofresponsibilityby Francis A. Honoré.en_US
dc.format.extent131 p.en_US
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technologyen_US
dc.rightsM.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.en_US
dc.rights.urihttp://dspace.mit.edu/handle/1721.1/7582
dc.subjectElectrical Engineering and Computer Science.en_US
dc.titleEnergy-aware architectures, circuits and CAD for field programmable gate arraysen_US
dc.title.alternativeEnergy-aware reconfigurable logic arrayen_US
dc.typeThesisen_US
dc.description.degreePh.D.en_US
dc.contributor.departmentMassachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.en_US
dc.identifier.oclc133167971en_US


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