The integration of InP /InGaAsP ridge waveguide structures with dielectric waveguides on silicon
Author(s)Barkley, Edward R. (Edward Robert)
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Clifton G. Fonstad.
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Chip-to-chip optical interconnect technology, which is being explored as a potential replacement for copper chip-to-chip interconnects at data transmission rates exceeding 10 Gb/s, is one of several technologies that could be enabled by the monolithic integration of III-V optoelectronic devices on a silicon integrated circuit. Two significant capabilities required to achieve this monolithic integration were addressed: the assembly of III-V device structures on silicon and the fabrication of the waveguides that perform the intra-chip routing of the optical signal to and from these integrated device structures. These waveguides, consisting of a silicon oxynitride core (n = 1.6) and a silicon dioxide cladding (n = 1.45) were deposited via plasma-enhanced chemical vapor deposition (PECVD). The integrated InP/InGaAsP structures were fabricated using an existing novel technique for preparing very thin (on the order of 5 pm thick) substrate free rectangular structures (approximately 145 pm wide by 300 pm long) with cleaved facets. Using a pick-and-place method, the InP/InGaAsP structures were assembled in 6 pm deep rectangular wells formed by etching through the waveguide stack. The resulting configuration of the integrated devices in the wells facilitated end-fire coupling with the silicon oxynitride waveguides.(cont.) Transmission spectrum measurements for this configuration verified the desired end-fire optical coupling through the integrated InP/InGaAsP device structures with a total coupling loss of 17.75 dB. This loss was shown through measurements and finite difference time domain (FDTD) simulations to be a function of integrated device misalignment, silicon oxynitride waveguide design, length of the gaps between the etched well edges and the device facets, and the well etch properties. Based on FDTD simulations and device misalignment statistics, it was shown that realistic, feasible improvements in the device alignment coupled with the use of higher index contrast waveguides could lower the coupling loss to 3.25 dB.
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, February 2007.Includes bibliographical references (p. 261-271).
DepartmentMassachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology
Electrical Engineering and Computer Science.