Parallel integrated receivers for multiple antenna wireless LAN systems

Abstract

This thesis focuses on the design of power- and area-efficient parallel integrated receivers for multiple antenna wireless LAN systems. These receivers are part of an indoor parallel radio system that achieves 1 gigabit per second data rates and enables high bandwidth wireless communication between portable user devices and a high speed wired internet connection. Since a critical aspect for efficiency is that an optimal number of transceivers be used to meet system requirements, this thesis first considers power dissipation and area. consumption for parallel integrated transceivers. It develops parallel transceiver power dissipation and area consumption models that are functions of distance, data rate, and noise figure and incorporate the behavior of a multiple-input, multiple-output channel and power dissipation and area consumption values for typical RF circuits. These models properly balance benefits of multiple antennas with drawbacks due to parallel radio overhead. Their application shows that the combined transceiver power dissipation can actually decrease with more antennas and also provides a circuits-based number of antennas upper bound that has not been established previously.

(cont.) The thesis then proposes a solution that applies multiple antenna signal-to-noise ratio (SNR) gain at the receiver to reduce its power dissipation and area consumption. SNR gain trades noise figure for power- and area-efficient circuits. The implementation of a, single chip 5.22-GHz area-efficient parallel receiver RFIC that shows practical application of these models, SNR gain, and area-efficient circuits is demonstrated. The context of this design comes from the Wireless Gigabit Local Area Network (WiGLAN). It's system characteristics such as a wide 150 MHz bandwidth and parallel radios uniquely determine a WiGLAN parallel receiver design.