Through-substrate interconnects for 3-D integration and RF systems

Abstract

Interconnects on silicon chips are fabricated on the top surface with an ever-increasing number of metal layers necessary to just meet performance needs. While devices have scaled according to Moore's law, interconnects have lagged. As metal line widths shrink and line lengths increase, parasitic resistance, capacitance, and inductance degrade circuit performance by increasing delays, loading, and power consumption. Separately, silicon has been supplanting GaAs in low-end, consumer RF applications. Improving the high-frequency performance of silicon by reducing ground inductance will project silicon technology into high-end RF and mm-wave applications. Furthermore, silicon-based systems allow for integration with digital blocks for system-on-chip (SoC). However, this introduces digital noise into the substrate, which interferes with the operation of RF/analog circuits. To address these challenges, we have developed a low-impedance, high-aspect ratio, through-substrate interconnect technology in silicon. Through-substrate vias exploit the third dimension by connecting the front to the backside of a chip so that power, ground, and global signals can be routed on the backside. Substrate vias can also be used to connect chip stacks in system-in-package designs.

(cont.) They also provide a low-inductance ground for RFICs and enable a novel way to reduce substrate noise for SoC. The fabrication process features backside patterning for routing of different signals on the back of the chip. Fabricated through-substrate vias were fully characterized using S parameters measured up to 50 GHz. The via resistance, inductance, and sidewall capacitance were extracted from these measurements. We report record-low inductance for high-aspect ratio vias, via resistance less than 1 R, and sidewall capacitance that approaches theory. We have also examined the application of substrate vias arranged as a Faraday cage to reduce substrate noise for SoC. The Faraday cage is exceptional in suppressing substrate crosstalk, especially at high frequencies: 32 dB better than the reference at 10 GHz, and 26 dB at 50 GHz, at a distance of 100 jim. To better understand its performance, we developed a lumped-element, equivalent circuit model. Simulations show that the circuit model accurately represents the noise isolation characteristics of the Faraday cage. Finally, Faraday cage design guidelines for optimum noise isolation are outlined.