Study of CMOS process variation by multiplexing analog characteristics
Author(s)Gettings, Karen Mercedes González-Valentín
Study of complementary metal oxide semiconductor process variation by multiplexing analog characteristics
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Duane S. Boning.
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Aggressive technology scaling raises the need for efficient methods to characterize and model circuit variation at both the front and back end of line, where critical parameters such as threshold voltage and parasitic capacitance must be carefully modeled for accurate circuit performance. This thesis addresses this need by contributing a test circuit methodology for the extraction of spatial, layout and size dependent variations at both device and interconnect levels. The test chip uses a scan chain approach combined with low-leakage and low-variation switches, and Kelvin sensing connections, providing access to detailed analog device characteristics in large arrays of test devices. Front end of line (FEOL) test structures include transistors of different sizes, number of polysilicon fingers, polysilicon fingers proximity, and orientation, for both NMOS and PMOS MOSFETs. Back end of line (BEOL) test structures include parasitic coupling, plane to plane and crossover capacitances, measured using a charge-based capacitive measurement (CBCM) methodology integrated with switches in the scan chain. The testing of the designed test chip has proven successful for both device and interconnect test structures.(cont.) Different layout practices in both NMOS and PMOS transistors are seen to result in significant differences in mean and standard deviation of measured output current, with 95% confidence or more. The FEOL structure analysis shows strong dependencies between layout practices: orientation offers a consistent but opposite offset in NMOS and PMOS transistors and variation increases for gate lengths split among fingers. Variation due to sizing follows Pelgrom's model, showing that variation increases for smaller gate lengths and widths, in both NMOS and PMOS transistors. Threshold voltage extraction and variation analysis also demonstrate how variation increases for smaller features. BEOL capacitances were extracted and sub-femto Farad changes were detected for capacitive test structures. Spatial analysis reveals a large die-to-die trend in device performance. The parameter extraction and variation analyses made possible by the variation test chip enable the identification of likely variation sources, quantification of circuit impact and sensitivity, and specification of layout practices for variation minimization.
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.Includes bibliographical references (p. 149-152).
DepartmentMassachusetts Institute of Technology. Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology
Electrical Engineering and Computer Science.