Design, fabrication, and characterization of germanium MOSFETs with high-k gate dielectric stacks based on the nitride interfacial layers
Author(s)Ritenour, Andrew P. (Andrew Paul), 1974-
Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Dimitri A. Antoniadis.
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To improve source injection velocity, and consequently MOSFET performance, high mobility semiconductors are being explored as possible replacements for silicon. Germanium offers enhanced electron mobility and superior hole mobility at high inversion charge density; however, the formation of a high quality germanium-dielectric interface remains a serious challenge. High-k dielectrics deposited directly on germanium exhibit poor physical and electrical properties so an interfacial layer is required. Proposed interlayers include GeON, Si, and metal nitrides such as AIN and Hf3N4. This work focuses on the fabrication and characterization of germanium MOSFETs with GeON, Hf3N4, and AIN interlayers. WN/A1203/AIN gate stacks deposited by atomic layer deposition (ALD) were investigated in detail. The impact of AIN interlayer thickness and post-metal anneal conditions on the electrical properties of WN/A1203/AIN/Ge capacitors was determined. Optimal capacitance-voltage characteristics were achieved for an AIN thickness of 2.5 nm and 450-500 °C post-metal annealing. Ge n- and p-MOSFETs were fabricated with GeON, AIN, and Hf3N4 interlayers. The hole mobility of these devices generally matched or exceeded silicon universal hole mobility; however, Ge n-FETs showed poor electron mobility (50-100 cm2/Vs). Many theories have been proposed to explain the low carrier mobility of Ge n-FETs. These theories were investigated and it was found that an asymmetric distribution of interface states in the bandgap is the primary cause of low electron mobility for germanium-A1N interfaces. The interface state density near the conduction band edge approaches 6x1013 cm-2 eVl, approximately 5x higher than near the valence band edge.(cont.) Low temperature characterization of n-FETs revealed degraded electron mobility due to carrier trapping and coulomb scattering from charged interface states. To reduce the interaction of carriers with interface states, n- and p-MOSFETs with reduced vertical effective field were fabricated using ion implantation. Devices exhibiting buried channel behavior showed electron and hole mobilities of 600 and 300 cm2/Vs respectively, confirming that mobility degradation is caused by interface states. Evidence for phosphorus passivation of the germanium-A1N interface is also presented.
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.Includes bibliographical references (p. 145-151).
DepartmentMassachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.
Massachusetts Institute of Technology
Electrical Engineering and Computer Science.