The Assq Chip and Its Progeny
Name
AI_WP_225.pdf
Description
Main article
Size
1.81 MB
Format
Adobe PDF
Checksum (MD5)
71b46098ba9d0f72f415a7e40171d62b
Author(s)
Agre, Philip E.
Date Issued
January 1982
Publisher
MIT Artificial Intelligence Laboratory
Series/Report no.
MIT Artificial Intelligence Laboratory Working Papers, WP-225
Abstract
The Assq Chip lives on the memory bus of the Scheme-81 chip of Sussman et al and serves as a utility for the computation of a number of functions concerned with the maintenance of linear tables and lists. Motivated by a desire to apply the design methodology implicit in Scheme-81, it was designed in about two months, has a very simple architecture and layout, and is primarily machine-generated. The chip and the design process are described and evaluated in the context of a proposal to construct a Scheme-to-silicon compiler that automates the design methodology used in the Assq Chip.
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