dc.contributor.advisor | Arvind. | en_US |
dc.contributor.author | Lin, Chun-Chieh | en_US |
dc.contributor.other | Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science. | en_US |
dc.date.accessioned | 2008-05-19T16:05:59Z | |
dc.date.available | 2008-05-19T16:05:59Z | |
dc.date.copyright | 2007 | en_US |
dc.date.issued | 2007 | en_US |
dc.identifier.uri | http://hdl.handle.net/1721.1/41656 | |
dc.description | Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007. | en_US |
dc.description | Includes bibliographical references (p. 75). | en_US |
dc.description.abstract | In this thesis, I present a implementation of a H.264 decoder designed in Bluespec SystemVerilog, a high level hardware description language. This design is intended to serve both as a more understandable reference code, as well as a starting point for efficient hardware implementations. I illustrate this by modifying this initial design to meet a performance requirement of 720p at 60 frames per second. | en_US |
dc.description.statementofresponsibility | by Chun-Chieh Li. | en_US |
dc.format.extent | 75 p. | en_US |
dc.language.iso | eng | en_US |
dc.publisher | Massachusetts Institute of Technology | en_US |
dc.rights | M.I.T. theses are protected by
copyright. They may be viewed from this source for any purpose, but
reproduction or distribution in any format is prohibited without written
permission. See provided URL for inquiries about permission. | en_US |
dc.rights.uri | http://dspace.mit.edu/handle/1721.1/7582 | en_US |
dc.subject | Electrical Engineering and Computer Science. | en_US |
dc.title | Implementation of H.264 Decoder in Bluespec SystemVerilog | en_US |
dc.type | Thesis | en_US |
dc.description.degree | M.Eng. | en_US |
dc.contributor.department | Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science | |
dc.identifier.oclc | 219733601 | en_US |