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dc.contributorSong, William S.en_US
dc.contributorMusicus, Bruce R.en_US
dc.date.accessioned2004-03-02T18:30:10Z
dc.date.available2004-03-02T18:30:10Z
dc.date.issued1990en_US
dc.identifier.otherNo. 503en_US
dc.identifier.urihttp://hdl.handle.net/1721.1/4200
dc.descriptionAlso issued as Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1989.en_US
dc.descriptionIncludes bibliographical references (p. 141-143).en_US
dc.description.sponsorshipSupported in part by U.S. Air Force Office of Scientific Research. AFOSR 86-0164 Supported in part by Charles S. Draper Laborarory. DL-H-404158en_US
dc.description.statementofresponsibilityWilliam S. Song and Bruce R. Musicus.en_US
dc.format.extent143 p.en_US
dc.format.extent12929925 bytes
dc.format.mimetypeapplication/pdf
dc.language.isoengen_US
dc.publisherMassachusetts Institute of Technology, Research Laboratory of Electronicsen_US
dc.relation.ispartofseriesTechnical report (Massachusetts Institute of Technology. Research Laboratory of Electronics) ; 552.en_US
dc.subject.lccTK7855.M41 R43 no.552en_US
dc.titleA fault-tolerant multiprocessor architecture for digital signal processing applicationsen_US


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