Effects of mechanical properties on the reliability of Cu/low-k metallization systems

Abstract

Cu and low-dielectric-constant (k) metallization schemes are critical for improved performance of integrated circuits. However, low elastic moduli, a characteristic of the low-k materials, lead to significant reliability degradation in Cu-interconnects. A thorough understanding of the effects of mechanical properties on electromigration induced failures is required for accurate reliability assessments. During electromigration inside Cu-interconnects, a change in atomic concentration correlates with a change in stress through the effective bulk modulus of the materials system, B, which decreases as the moduli of low-k materials used as inter-level dielectrics (ILDs) decrease. This property is at the core of discussions on electromigration-induced failures by all mechanisms. B is computed using finite element modeling analyses, using experimentally determined mechanical properties of the individual constituents. Characterization techniques include nanoindentation, cantilever deflection, and pressurized membrane deflection for elastic properties measurements, and chevron-notched double-cantilever pull structures for adhesion measurements. The dominant diffusion path in Cu-interconnects is the interface between Cu and the capping layer, which is currently a Si3N4-based film. We performed experiments on Cu-interconnect segments to investigate the kinetics of electromigration. A steady resistance increase over time prior to open-circuit failure, a result of void growth, correlates with the electromigration drift velocity. Diffusive measurements made in this fashion are more fundamental than lifetime measurements alone, and correlate with the combined effects of the electron wind and the back stress forces during electromigration induced void growth.

(cont.)Using this method, the electromigration activation energy was determined to be 0.80±0.06eV. We conducted experiments using Cu-interconnects with different lengths to study line length effects. Although a reliability improvement is observed as the segment length decreases, there is no deterministic current-density line-length product, jL, for which all segments are immortal. This is because small, slit-like voids forming directly below vias will cause open-failures in Cu-interconnects. Therefore, the probabilistic jLcrit values obtained from via-above type nterconnects approximate the thresholds for void nucleation. The fact that jLcrit,nuc monotonically decreases with B results from an energy balance between the strain energy released and surface energy cost for void nucleation and the critical stress required for void nucleation is proportional to B. We also performed electromigration experiments using Cu/low-k interconnect trees to investigate the effects of active atomic sinks and reservoirs on interconnect reliability. In all cases, failures were due to void growth. Kinetic parameters were extracted to be ... Quantitative analysis demonstrates that the reliability of the failing segments is modulated by the evolution of stress in the whole interconnect tree. During this process, not only the diffusive parameters but also B play critical roles. However, as B decreases, the positive effects of reservoirs on reliability are diminished, while the negative effects of sinks on reliability are amplified.

(cont.) Through comprehensive failure analyses, we also successfully identified the mechanism of electromigration-induced extrusions in Cu/low-k interconnects to be nearmode-I interfacial fracture between the Si3N4-based capping layer and the metallization/ILD layer below. The critical stress required for extrusion is found to depend not only on B but also on the layout and dimensions of the interconnects. As B decreases, sparsely packed, wide interconnects are most prone to extrusion-induced failures. Altogether, this research accounts for the effects of mechanical properties on all mechanisms of failure due to electromigration. The results provide an improved experimental basis for accurate circuit-level, layout-specific reliability assessments.