Graph-based representations and coupled verification of VLSI schematics and layouts

Author(s)
Bamji, Cyrus S.
Thumbnail
DownloadRLE-TR-547-20860899.pdf (11.67Mb)
Metadata
Show full item record
Description
Includes bibliographical references (p. 199-202).
Date issued
1989
URI
http://hdl.handle.net/1721.1/4205
Publisher
Research Laboratory of Electronics, Massachusetts Institute of Technology
Other identifiers
no. 547
Series/Report no.
Technical report (Massachusetts Institute of Technology. Research Laboratory of Electronics) ; 547.
Collections