Nano-scale scratching in chemical-mechanical polishing

Abstract

During the chemical-mechanical polishing (CMP) process, a critical step in the manufacture of ultra-large-scale integrated (ULSI) semiconductor devices, undesirable nano-scale scratches are formed on the surfaces being polished. As the width of the interconnect Cu lines continues to shrink to below 60 nm, and as the traditional Si02 dielectric is replaced by the compliant, lowdielectric-constant materials, scratching has emerged as a challenging problem. This thesis presents a contact mechanics based approach for modeling nano-scale scratching by the hard abrasive particles in the slurry. Single-particle models that use elastic and plastic analyses to determine both the lower- and upper-bounds for the load per particle are introduced. These bounds are established for both homogenous and composite coatings. Multi-particle models are also presented. These models use contact mechanics at the pad-particle-coating interface to relate the global parameters of CMP, such as pressure, particle radius, slurry volume fraction and the material and geometrical properties of the pad and coating, to the widths and depths of scratches in the coatings. A lower- and upper-limit for the scratch width and depth in CMP is defined. Controlled indentation and scratching experiments have been conducted using a Hysitron TriboIndenter to validate the single-particle models. Based on these experiments, the upper-bound load per particle is used to predict the widths and depths of scratches in coatings. Furthermore, polishing experiments have been conducted using a CMP tool to validate the limits. The upper-limit for the semi-width of a scratch is equal to the product of the particle radius and the square root of the ratio of pad hardness to coating hardness. For a typical CMP pad and Cu coating, this upper-limit is one-fifth of the particle radius. Based on the models and the experiments, practical solutions for mitigating scratching in CMP, especially Cu CMP, are suggested.