Substrate engineering for monolithic integration of III-V semiconductors with Si CMOS technology
Author(s)Dohrman, Carl Lawrence
Massachusetts Institute of Technology. Dept. of Materials Science and Engineering.
Eugene A. Fitzgerald.
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Ge virtual substrates, fabricated using Si1-xGex-.Ge, compositionally graded buffers, enable the epitaxial growth of device-quality GaAs on Si substrates, but monolithic integration of III-V semiconductors with Si CMOS using this platform is hampered by the large thickness of the Si1-xGex graded region. To address this issue, the Silicon on Lattice-engineered Silicon (SOLES) was developed, consisting of a silicon-on-insulator (SOI) structure fabricated on a Ge virtual substrate. Placement of the Si device layer at the surface makes it possible to process this platform similarly to typical SOI wafers, with the added functionality of a buried III-V template which can be used for GaAs device fabrication. This platform was fabricated using a scalable layer transfer technique. AlInGaP LEDs were also demonstrated on a SOLES substrate. In addition, an alternative growth process was investigated for Si1-xGex virtual substrates with lower threading dislocation density (TDD) and thickness. This process, the thermally relaxed ultra-thin (TRUT) buffer process, consists of coherent growth of lattice-mismatched Si1.xGex layers, followed by post-growth annealing. Growth of TRUT buffers over the Si0.5Ge0.5 to Si0.3Ge0.7 alloy range with high strain levels resulted in the nucleation of surface defects which appear to limit the maximum strain rate of compositionally graded buffers. However, application of the TRUT process in the Si0.1Ge0.9 to Ge alloy range resulted in relaxed Ge virtual substrates with a 59% reduction in TDD compared to conventional processes. Lastly, growth of high-quality lattice-matched GaAsyP1.y on Si0.5Ge0.5, Si0.3Geo.7, and Si0.2Ge0.8 virtual substrates was investigated.(cont.) Adaptation of standard GaAs on Ge processes to this heteroepitaxial system resulted in mostly non-planar growth (similar to typical GaP growth on Si) with only limited regions of planar GaAsyP1-y layers on Si0.2Ge0.8 virtual substrates. Planar growth of GaAsyP1-y on Si0.3Ge0.7 virtual substrates was enabled by minimizing the atmospheric exposure of the Si0.3Ge0.7 as it is transferred between growth reactors, establishing that the GaAsyP1-y growth process on Si1-xGex is strongly affected by atmospheric contaminants. Further minimization of air exposure, through use of Si1-xGex homoepitaxial buffers and growth of Si1-xGex and GaAsyP1-y in a single reactor, is expected to further improve epitaxial quality across the entire lattice-matched GaAsyP1-y/Si1-xGex range, including GaP on Si.
Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2008.Includes bibliographical references (p. 165-172).
DepartmentMassachusetts Institute of Technology. Dept. of Materials Science and Engineering.
Massachusetts Institute of Technology
Materials Science and Engineering.