Technology and market evaluation for semiconductor nanowire transistors

Abstract

Information processing systems have been getting more powerful over the course of the past three decades due to the scaling of transistor dimensions. Scaling of transistor dimension causes a plethora of technological problems if pursued in the current fashion. Gate-All-Around architecture for transistors has been shown to alleviate many of the problems posed by scaling. Silicon being the material of choice of the semiconductor industry, it is highly desirable to have silicon one dimensional channel in the Gate-All- Around transistor. Silicon nanowires have been fabricated using various methods, in this work Self-Limiting-Oxidation was analyzed for its technological feasibility and found to be satisfactory. Possible value propositions and IP landscape analysis show that this methodology is very much feasible. As the new architecture essentially solves the problems that arise due to aggressive scaling, it becomes vital to look at the relevance of scaling beyond 45 nm technology node. Careful analysis of the semiconductor industry breakdown and top semiconductor foundries' financials reveal that scaling might not be pursued as aggressively as expected. The relevance of Moore's law in the current scheme of things could be that of a Self-fulfilling prophecy. Given this climate, Self Limiting Oxidation based Silicon nanowires have better commercial potential in the field of sensors. Monolithic integration and superior spatial precision makes this methodology ideally suited to the needs of applications which include many different kinds of sensors on the same Lab-on-Chip.